The present invention relates generally to xe2x80x9cvirtualxe2x80x9d channel memories, and more particularly to the testing of such memories.
Many computer systems can include a main storage. Typically, a main storage can include high capacity semiconductor devices that are relatively inexpensive. One such semiconductor device is a general purpose dynamic random access memories (DRAMs). A drawback to general purpose DRAMs is that such devices can have relatively slow operating speeds.
More recent computer systems can have increased operating speeds. In particular, computer system microprocessor unit (MPU) speeds have increased. While general purpose DRAM speeds have also increased, such increases in speed have generally not been sufficient to keep up with MPU speeds. Due to such operating speed differences, mainstream systems are usually equipped with a substorage device between a main storage and a MPU. Such substorage devices are typically referred to as xe2x80x9ccachexe2x80x9d memories. A cache memory can utilize a high-speed static RAM (SRAM), an emitter coupled logic bipolar RAM (ECLRAM), or other such storage devices.
A cache memory may be external to a MPU or may be built within a MPU. Recently however, some workstations or personal computers have included a semiconductor storage device having a main storage device formed from a DRAM and a cache memory formed from a high-speed SRAM. The DRAM and SRAM are formed on the same semiconductor substrate.
Prior art semiconductor devices have been disclosed in Japanese Patent Laid-Open Publication No. Sho 57-20983, Japanese Patent Laid-Open Publication No. Sho 60-7690, Japanese Patent Laid-Open Publication No. Sho 62-38590, Japanese Patent Laid-Open Publication No. Hei 1-146187. Since devices that include a DRAM and SRAM can use the SRAM as a cache, such devices are often referred to as cache DRAMs or CDRAMs.
CDRAMs can be arranged to transfer data between the DRAM and SRAM parts in a bi-directional fashion. When a memory is accessed, if the requested data location is in the SRAM portion, the access can be considered a cache xe2x80x9chit.xe2x80x9d If a requested data location is not in the SRAM portion, the access can be considered a cache xe2x80x9cmiss.xe2x80x9d A drawback to conventional CDRAMs is that a cache miss can result in a data transfer operation that can include some delay.
A number of prior art techniques have been proposed to address the above drawback to CDRAMs. A number of prior art semiconductor devices are set forth in Japanese Patent Laid-Open Publication Hei 4-252486, Japanese Patent Laid-Open Publication Hei 4-318389, and Japanese Patent Laid-Open Publication Hei 5-2872. These publications disclose CDRAMs having bi-directional transfer gate circuits between a DRAM portion and a SRAM portion. The bi-directional transfer gate circuits can have a latch or register function. With a latch or register function it can be possible to perform a data transfer from the SRAM portion to the DRAM portion and a data transfer from the DRAM portion to the SRAM portion at the same time.
Despite the advantages of the above references, such as Japanese Patent Laid-Open Publication Hei 4-318389 and the like, such approaches can have problems. One such problem is pin count. Because the DRAM portion and SRAM portion have their own respective address pins, the number of pins on a CDRAM can be much larger than those of a conventional DRAM. Therefore, a CDRAM device is not compatible with an ordinary DRAM or the like.
A second problem associated with conventional CDRAMs is the amount of area that may be needed to realize a data transfer circuit. Because the area available for such circuits can be limited, the number of transfer bit lines between a DRAM and SRAM portion can also be limited.
Due to the above constraints, the number of data bits that can be transferred at the same time between a DRAM portion and an SRAM portion on a CDRAM can be limited. As one example, the number of bits can be limited to 16 bits. Further, many CDRAMs avoid placing transfer lines in the same area as column select lines. As a result, the number of transfer lines can further be limited, as the available areas for such lines can have a limited width. As a general rule, the smaller the number of bits that can be transferred between DRAM and SRAM portions, the lower hit rate of the cache. One skilled in the art would recognize that lower cache hit rates lead to slower overall data access operations for a CDRAM.
One skilled in the art would recognize that a main storage can receive memory accesses from different controllers (masters). Such multiple masters can also adversely impact system speed. In order to increase the speed of a system without lowering the hit rate of a cache, even in the case of multiple masters, a novel virtual channel SDRAM. (VCSDRAM) has been developed by the present inventor. Such a VCSDRAM can include a main storage portion and a substorage portion. The substorage portion can be allocated into a plurality of access registers. Reference is made to Japanese Patent Laid-Open Publication Hei 11-86559 and Japanese Patent Laid-Open Publication Hei 11-86532.
Referring now to FIG. 9, a VCSDRAM according to the present inventor is set forth in a block schematic diagram. The VCSDRAM of FIG. 9 is designated by the general reference character 900, and is shown to include a command decoder circuit 902, a main storage activating signal generating circuit 904, a transfer operation start signal generating circuit 906, a transfer operation control circuit 908, an operation mode setting circuit 910, a main storage control circuit 912, a main storage portion 914, a substorage portion 916, and a data transfer portion 918.
The command decoder circuit 902 can receive four command signals RASB, CASB, WEB and CSB as inputs, and generate a number of internal signals. Internal signals can include an active command signal 120, a precharge command signal 122, and a transfer command signal 124.
The main storage activating signal generating circuit 904 can receive an active command signal 120 and a precharge command signal 122 and provide a main storage activating signal 128.
The transfer operation start signal generating circuit 906 can receive a transfer command signal 124 and provide a transfer operation start signal 130.
The transfer operation control circuit 908 can receive a transfer operation start signal 130 and provide a storage control signal 132 that can control a substorage portion 916 and a data transfer portion 918. Once a data transfer operation has ended, the transfer operation control circuit 908 can activate a transfer reset signal 134 that is connected to the transfer operation start signal generating circuit 906. An active transfer reset signal 134 can release the latched state of a transfer command within the transfer operation start signal generating circuit 906.
The operation of the VCSDRAM will now be described in conjunction with FIG. 4. FIG. 4 is a timing diagram illustrating the operation of a VCSDRAM.
A command decoder circuit 902 can receive an active command, shown as xe2x80x9c401,xe2x80x9d and output an active command signal 120. The main storage activating signal generating circuit 904 can receive the active command signal 120 and provide a main storage activating signal 128 on the basis of the active command signal 120.
Next, a command decoder circuit 902 can receive a transfer command, shown as xe2x80x9c402,xe2x80x9d and output a transfer command signal 124.
The transfer operation start signal generating circuit 906 can receive a transfer command signal 124. The transfer command signal 124 can be latched and held, and a transfer operation start signal 130 can be activated (driven high).
Next, a transfer operation control circuit 908 can receive an active transfer operation start signal 130 and activate a storage control signal 132 (drive it high). The storage control signal 132 can control the substorage portion 916 and control the transfer of data by the data transfer portion 918.
When a storage control signal 132 is activated, the main storage control circuit 912 and data transfer portion 918 can be activated. The data transfer portion 918 can perform a data transfer operation between a main storage portion 914 and substorage portion 916.
Once a data transfer operation between a main storage portion 914 and a substorage. portion 916 has ended, the transfer operation control circuit 908 can activate a transfer reset signal 134.
An active transfer reset signal 134 can be received by the transfer operation start signal generating circuit 906. In response to the active transfer reset signal 134, a transfer command that is latched within the transfer operation start signal generating circuit 906 is released, resulting in the transfer operation start signal 130 being deactivated (low).
FIG. 4 also illustrates a time period T0. T0 can represent the period of an external clock signal CLK. Another time period is shown as Td. Td can represent the interval between the activation of a main storage portion 914 by a main storage control circuit 912 and the time when a data transfer operation takes place in response to a storage control signal 132.
It is noted that in a VCSDRAM such as that set forth in FIG. 9, the duration of the Td time period can affect the operation of the VCSDRAM. For example, a Td time that is too short can lead to insufficient amplification of memory cell data within a main storage portion 914. One skilled in the art would recognize that insufficient amplification of memory cell data can lead to erroneous read and/or write operations. Further, the shorter a Td time, the more likely fluctuations in a power supply voltage (such as a high power supply voltage and a ground supply potential) will adversely affect the operation of the VCSDRAM.
The Td time for a VCSDRAM can result in VCSDRAMs being tested for a minimum Td time specification. Because VCSDRAMs can have high frequency operating speeds, to ensure a Td specification, a high frequency test machine can be used. A drawback to high frequency test machines is that such machines can be expensive.
An object of the present invention is to provide a virtual channel synchronous dynamic random access memory (VCSDRAM) that can be tested for a high frequency operation with test machines of relatively low frequency. Such low frequency test machines can be less expensive than high frequency test machines.
To achieve the above-mentioned object, a VCSDRAM according to one embodiment of the present invention can include a main storage portion and a substorage portion. Data can be transferred between the main storage portion and the substorage portion according to a transfer operation start signal. The VCSDRAM can further include a command decoder and a transfer operation start signal generator.
A command decoder circuit can decode external command signals and generate internal control signals including at least an active command signal, a precharge signal, and a transfer command signal. An active command signal can generate a main storage activating signal.
A transfer operation start signal generating circuit can latch a transfer command signal and output a transfer operation start signal. A transfer operation start signal can be output according to a main storage activating signal and reset by a transfer reset signal. A transfer reset signal can be activated after a data transfer operation has ended.
Within a transfer operation start signal generating circuit, a latch which latches a command signal can be released by a precharge command signal or by a mode register set command signal, or by both of these signals.
According to one aspect of an embodiment, the release of a latch by a precharge command signal or a mode register set signal can occur at the time power is provided to a VCSDRAM.
A VCSDRAM according to another embodiment can include a main storage portion and a substorage portion. Data can be transferred between the main storage portion and the substorage portion according to a transfer operation start signal. The VCSDRAM can further include a command decoder, a transfer operation start signal generator, and a transfer operation control circuit.
A command decoder circuit according to the above embodiment can decode external command signals and generate internal control signals including at least an active command signal, a precharge signal, and a transfer command signal. An active command signal can generate a main storage activating signal.
A transfer operation start signal generating circuit according to the above embodiment can latch a transfer command signal and output a transfer operation start signal. A transfer operation start signal can be output according to a main storage activating signal and reset by a transfer reset signal. A transfer reset signal can be activated after a data transfer operation has ended.
A transfer operation control circuit according to the above embodiment can receive a transfer operation start signal and generate a control signal. The control signal can control the transfer of data between the main storage portion and the substorage portion.
According to one aspect of the above embodiment, a VCSDRAM can further include a main storage activating signal generating circuit that can receive an active command signal and a precharge command signal from the command decoder circuit and provide a main storage activating signal.
According to another aspect of the above embodiment, when power is applied to the VCSDRAM, the command decoder circuit can generate a precharge command signal or a mode register set command signal, or both. Such signals can initialize the transfer operation start signal generating circuit.